HC705V8GRSSLASHD datasheet(46/172 Pages) NXP

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SECTION 5: INTERRUPTS

Page 35

MC68HC705V8 Specification Rev. 2.1

SECTION 5

INTERRUPTS

The MCU can be interrupted seven different ways:

1. Nonmaskable Software Interrupt Instruction (SWI)

2. External Asynchronous Interrupt (IRQ)

3. External Interrupt via IRQ on PA0-PA7, PC0-PC7

4. Internal 16-bit Timer Interrupt (TIMER)

5. Internal Serial Peripheral Interface Interrupt (SPI)

6. Internal MDLC Interrupt (MDLC)

7. Internal 8-bit Timer Interrupt

5.1

CPU INTERRUPT PROCESSING

Interrupts cause the processor to save register contents on the stack and to set the interrupt

mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not

cause the current instruction execution to be halted, but are considered pending until the

current instruction is complete.

If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt

enable bit is set the processor will proceed with interrupt processing. Otherwise, the next

instruction is fetched and executed. If an interrupt occurs the processor completes the

current instruction, then stacks the current CPU register states, sets the I-bit to inhibit

further interrupts, and finally checks the pending hardware interrupts. If more than one

interrupt is pending following the stacking operation, the interrupt with the highest vector

location shown in Table 5-1 will be serviced first. The SWI is executed the same as any

other instruction, regardless of the I-bit state.

When an interrupt is to be processed the CPU fetches the address of the appropriate

interrupt software service routine from the vector table at locations $3FF2 through $3FFF

as deﬁned in Table 5-1.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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