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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HC705RC17GRS/D bảng dữ liệu(PDF) 99 Page - NXP Semiconductors |
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HC705RC17GRS/D bảng dữ liệu(HTML) 99 Page - NXP Semiconductors |
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99 / 126 page  Instruction Set Addressing Modes MC68HC705RC17 — Rev. 2.0 General Release Specification Instruction Set 12.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 12.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 12.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 12.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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