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HC705RC17GRS/D bảng dữ liệu(PDF) 18 Page - NXP Semiconductors |
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HC705RC17GRS/D bảng dữ liệu(HTML) 18 Page - NXP Semiconductors |
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18 / 126 page ![]() General Description General Release Specification MC68HC705RC17 — Rev. 2.0 General Description • Power-Saving Stop and Wait Modes • Programmable Options: – COP Watchdog Timer – STOP Instruction Disable – Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger – Port B Pullups for Keyscan • Illegal Address Reset • ROM Security NOTE: A line over a signal name indicates an active-low signal. For example, RESET is active low. 1.4 Options The options on the MC68HC705RC17 are handled with 11 EPROM bits in two separate mask option register (MOR1 and MOR 2). These options are: • Eight Port B Pullups • IRQ Sensitivity • COP Enable/Disable • STOP Enable/Disable The factory will program these options in the ROM versions of this device. 1.5 Signal Description Pinout for the 28-pin small outline integrated circuit (SOIC) package is shown in Figure 1-2. Pinout for the 28-pin plastic dual in-line (PDIP) package is shown in Figure 1-3. The signals are described in the following subsections. NOTE: Consult the factory for availability of higher pin count packages. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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