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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HC705RC17GRS/D bảng dữ liệu(PDF) 86 Page - NXP Semiconductors |
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HC705RC17GRS/D bảng dữ liệu(HTML) 86 Page - NXP Semiconductors |
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86 / 126 page  Phase-Locked Loop (PLL) Synthesizer General Release Specification MC68HC705RC17 — Rev. 2.0 Phase-Locked Loop (PLL) Synthesizer PLLON — PLL On This bit activates the synthesizer circuit without connecting it to the control circuit. This allows the synthesizer to stabilize before it can drive the CPU clocks. When this bit is cleared, the PLL is shut off and the BCS bit cannot be set. (Setting the BCS bit would engage the disabled PLL onto the bus). Reset sets this bit. NOTE: For minimum current consumption, disable the PLL module before entering wait mode. NOTE: The PLLON bit should not be cleared unless the BCS bit has been cleared on a previous write to the register. VCOTST — VCO Test NOTE: This bit is intended for use by Motorola. This bit cannot be cleared in user mode. PS1 and PS0 — PLL Synthesizer Speed Select These two bits select one of four taps from the PLL to drive the CPU clocks. These bits are used in conjunction with PLLON and BCS bits in the PLL control register. Reset clears PS1 and sets PS0, choosing a bus clock frequency of 524 kHz using an external crystal of 32.768 kHz. CAUTION: This bit should not be modified if BCS and PLLON in the PLLCR are both at a logic high. Table 10-1. PS1 and PS0 Speed Selects with 32.768-kHz Crystal PS1 PS0 CPU Bus Clock Frequency (fOP) 0 0 524 kHz 0 1 1.049 MHz Reset Condition 1 0 2.097 MHz For 3.0 V ≤ V DD ≤ 5.5 V 1 1 4.194 MHz Do Not Select Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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