ST20-GP6 datasheet(27/123 Pages) STMICROELECTRONICS

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4.6.3 Trap handlers

For each trap handler there is a trap handler structure and a trapped process structure. Both the

trap handler structure and the trapped process structure are in memory and can be accessed via

instructions, see section 4.6.4.

The trap handler structure speciﬁes what should happen when a trap condition is present, see

Table 4.5.

The trapped process structure saves some of the state of the process that was running when the

trap was taken, see Table 4.6.

In addition, for each priority, there is an

Enables register and a Status register. The Enables regis-

ter contains ﬂags to enable each cause of trap. The

Status register contains ﬂags to indicate which

trap conditions have been detected. The

Enables and Status register bit encodings are given in

Table 4.4.

A trap will be taken at an interruptible point if a trap is set and the corresponding trap enable bit is

set in the

Enables register. If the trap is not enabled then nothing is done with the trap condition. If

the trap is enabled then the corresponding bit is set in the

Status register to indicate the trap con-

dition has occurred.

When a process takes a trap the processor saves the existing

Iptr, Wptr, Status and Enables in

the trapped process structure. It then loads

Iptr, Wptr and Status from the equivalent trap handler

structure and ANDs the value in

Enables with the value in the structure. This allows the user to dis-

able various events while in the handler, in particular a trap handler must disable all the traps of its

trap group to avoid the possibility of a handler trapping to itself.

The trap handler then executes. The values in the trapped process structure can be examined

using the ldtrapped instruction (see section 4.6.4). When the trap handler has completed its opera-

Comments

Location

Iptr

Iptr of trap handler process.

Base + 3

Wptr

Wptr of trap handler process. A null Wptr indicates that a trap handler has not been installed. Base + 2

Status

Contains the

Status register that the trap handler starts with.

Base + 1

Enables

A word which encodes the trap enable and global interrupt masks, which will be ANDed with

the existing masks to allow the trap handler to disable various events while it runs.

Base + 0

Table 4.5 Trap handler structure

Comments

Location

Iptr

Points to the instruction after the one that caused the trap condition.

Base + 3

Wptr

Wptr of the process that was running when the trap was taken.

Base + 2

Status

The relevant trap bit is set, see Table 4.3 for trap codes.

Base + 1

Enables

Interrupt enables.

Base + 0

Table 4.6 Trapped process structure

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