EM6821 datasheet(8/68 Pages) EMMICRO

8 / 68 page

EM6821

www.emmicroelectronic.com

4. Reset

Figure 6. illustrates the reset structure of the EM6821. One can see that there are six possible reset sources :

(1) Internal initial reset from the Power On Reset (POR) circuitry.

--> POR

(2) External reset from the Reset terminal.

--> System Reset, Reset CPU

(3) External reset by simultaneous high/low inputs to port A.

--> System Reset, Reset CPU

(Combinations are defined in the registers OptInpRSel1 and OptInpRSel2)

(4) Internal reset from the Digital Watchdog.

--> System Reset, Reset CPU

(5) Internal reset from the Oscillation Detection Circuit.

--> System Reset, Reset CPU

(6) Internal reset when sleep mode is activated.

-->

System

Reset,

Reset CPU

All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the

system reset remains active long enough for all system functions to be reset (active for n system clock cycles).

The ‘CPU Reset Delay’ ensures that the reset CPU remains active until the oscillator is in stable oscillation.

As well as activating the system reset and the reset CPU, the POR also resets all option registers and the

sleep enable (SleepEn) latch. System reset and reset CPU do not reset the option registers nor the SleepEn

latch.

Reset state can be shown on Strobe terminal by selecting StrobeOutSel1,0 = 0 in RegLcdCntl1.

Figure 6. Reset Structure

S ystem R eset

Delay

CPU Reset

Delay

Enable

A ctivate

Digital

W atchdog

O scillation

Detection

R eset from Port A

Input C om bination

Reset P AD

Sleep

O ptInpR S leep

Reset

CP U

Inhibit

O scillation

Detection

Inhibit

Digital

W atchdog

PO R

PO R to O ption

R egisters & S leepEn

Latch

DEBO UNCE

Sleep

Latch

SleepEn

Latch

POR

Internal D ata B us

Write R eset

R ead S tatus

Write A ctive

R ead S tatus

Ck[10]

Ck[1]

Ck[8]

Ck[1]

C k[15]

PO R

Analogue

Filter

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