EM6821 datasheet(45/68 Pages) EMMICRO

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EM6821

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13. RAM

The EM6821 has two 64x4 bit RAM’s built-in.

The main RAM (RAM1) is direct addressable on addresses decimal(0 to 63). A second RAM (RAM2) is indirect

addressable on addresses 64,65, 66 and 67 together with the index from RegIndexAdr.

The RAM2 addressing is indirect using the RegIndexAdr value as an offset to the directly addressed base

RAM2_0, RAM2_1 , RAM2_2 or RAM2_3 registers.

To write or read the RAM2 the user has first to set the offset value in the RegIndexAdr register. The actual

access then is made on the RAM2 base addresses RAM2_0 , RAM2_1, RAM2_2 or RAM2_3. Refer to

Figure 34. Ram Architecture, for the address mapping.

i.e. Writing hex(5) to Ram2 add location 30: First write hex(E) to RegIndexAdr, then write hex(5) to RAM2_1

RAM Extension : Unused R/W Registers can often be used as possible RAM extension. Be careful not to use

memory.

In case of 3 times multiplex and using all the 20 Segment outputs you may have five additional 4 bit registers..

Also for each unused Segment output you may have one additional 4 bit register.

Figure 34. Ram Architecture

RAM1_63

RAM1_62

RAM1_61

RAM1_60

4 bit R/W

RegIndexAdr[F]

RegIndexAdr[E]

4 bit R/W

...

RegIndexAdr[1]

4 bit R/W

RegIndexAdr[0]

RAM1_0

4 bit R/W

RAM1_3

RAM1_2

RAM1_1

RAM2_3

RAM2_2

RAM2_1

4 bit R/W

RAM2_0

4 bit R/W

RegIndexAdr[F]

RegIndexAdr[E]

4 bit R/W

...

RegIndexAdr[1]

4 bit R/W

RegIndexAdr[0]

4 bit R/W

RegIndexAdr[F]

RegIndexAdr[E]

4 bit R/W

...

RegIndexAdr[1]

4 bit R/W

RegIndexAdr[0]

4 bit R/W

RegIndexAdr[F]

RegIndexAdr[E]

4 bit R/W

...

RegIndexAdr[1]

4 bit R/W

RegIndexAdr[0]

64 x 4 indexed addressable RAM2

64 x 4 direct addressable RAM1

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