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EM6620WS27 bảng dữ liệu(PDF) 32 Page - EM Microelectronic - MARIN SA

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EM6620
Copyright
© 2005, EM Microelectronic-Marin SA
32
www.emmicroelectronic.com
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their
corresponding mask setting and not on the general interrupt enable status. Whenever the EM6620 goes into
HALT Mode the IntEn bit is automatically set to 1, thus allowing to resume from Halt Mode with an interrupt.
9.1 Interrupt control registers
Table 9.1.1 Register RegIRQ1
Bit
Name
Reset
R/W
Description
3
IRQPA[3]
0
R/W*
Port A PA[3] interrupt request
2
IRQPA[2]
0
R/W*
Port A PA[2] interrupt request
1
IRQPA[1]
0
R/W*
Port A PA[1] interrupt request
0
IRQPA[0]
0
R/W*
Port A PA[0] interrupt request
W*; Writing of 1 clears the corresponding bit.
Table 9.1.2 Register RegIRQ2
Bit
Name
Reset
R/W
Description
3
IRQHz1
0
R/W*
Prescaler interrupt request
2
IRQHz32/8
0
R/W*
Prescaler interrupt request
1
IRQBlink
0
R/W*
Prescaler interrupt request
0
IRQPB0Comp
0
R/W*
Compare interrupt request
W*; Writing of 1 clears the corresponding bit.
Table 9.1.3 Register RegIRQ3
Bit
Name
Reset
R/W
Description
3
IRQVLD
0
R/W*
VLD interrupt request
2
IRQMSC
0
R/W*
Millisecond Counter int. request
1
IRQCount0
0
R/W*
Counter interrupt request
0
IRQCntComp
0
R/W*
Counter interrupt request
W*; Writing of 1 clears the corresponding bit.
Table 9.1.4 Register RegIRQMask1
Bit
Name
Reset
R/W
Description
3
MaskIRQPA[3]
0
R/W
Port A PA[3] interrupt mask
2
MaskIRQPA[2]
0
R/W
Port A PA[2] interrupt mask
1
MaskIRQPA[1]
0
R/W
Port A PA[1] interrupt mask
0
MaskIRQPA[0]
0
R/W
Port A PA[0] interrupt mask
Interrupt is not stored if the mask bit is 0.
Table 9.1.5 register RegIRQMask2
Bit
Name
Reset
R/W
Description
3
MaskIRQHz1
0
R/W
Prescaler interrupt mask
2
MaskIRQHz32/8
0
R/W
Prescaler interrupt mask
1
MaskIRQBlink
0
R/W
Prescaler interrupt mask
0
MaskIRQPB0Comp
0
R/W
Compare interrupt mask
Interrupt is not stored if the mask bit is 0.
Table 9.1.6 register RegIRQMask3
Bit
Name
Reset
R/W
Description
3
MaskIRQVLD
0
R/W
VLD interrupt mask
2
MaskIRQMSC
0
R/W
Millisecond Counter interrupt mask
1
MaskIRQCount0
0
R/W
Counter interrupt mask
0
MaskIRQCntComp
0
R/W
Counter interrupt mask
Interrupt is not stored if the mask bit is 0



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