EM6620WS27 datasheet(8/56 Pages) EMMICRO

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EM6620

www.emmicroelectronic.com

4. Reset

Figure 6 illustrates the reset structure of the EM6620. One can see that there are five possible reset sources :

(1) Internal initial reset from the Power On Reset (POR) circuitry.

--> POR

(2) External reset by simultaneous high/low inputs to port A.

--> System Reset, Reset CPU

(Combinations are defined in the registers OptInpRSel1 and OptInpRSel2

(3) Internal reset from the Digital Watchdog.

--> System Reset, Reset CPU

(4) Internal reset from the Oscillation Detection Circuit.

--> System Reset, Reset CPU

(5) Internal reset when SLEEP mode is activated.

--> System Reset, Reset CPU

All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the

system reset remains active long enough for all system functions to be reset (active for N system clock cycles).

The ‘CPU Reset Delay’ ensures that the Reset CPU remains active until the oscillator is in stable oscillation.

As well as activating the system reset and the Reset CPU, the POR also resets all option registers and the

sleep enable (SleepEn) latch. System reset and Reset CPU do not reset the option registers nor the sleep

enable latch.

Figure 6. Reset structure

System Reset

Delay

CPU Reset

Delay

Enable

Activate

Digital

W atchdog

Oscillation

Detection

Reset from port A Input

combination

NoInpReset

Sleep

Reset

CPU

Inhibit

Oscillation

detection

Inhibit

Digital

W atchdog

POR

POR to Option

Registers & SLEEP

ENABLE latch

DEBOUNCE

SLEEP

Latch

SLEEP

ENABLE

Latch

POR

Internal Data Bus

Write Reset

Read Status

Write Active

Read Status

CK[10]

CK[1]

ck[8]

ck[1]

ck[15]

POR

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