UPSD3422EB40U6 datasheet(285/300 Pages) STMICROELECTRONICS

285 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422, UPSD3433, UPSD3434, UPSD3454

DC and AC parameters

285/300

Figure 106. Peripheral I/O WRITE timing

Table 230.

Port A peripheral data mode READ timing (3 V PSD module)

Symbol

Parameter

Conditions

Min

Max

Turbo

off

Unit

tAVQV–PA

Address valid to data valid

(1)

Any input used to select Port A data peripheral mode.

+ 15

tSLQV–PA

CSI valid to data valid

+ 15

tRLQV–PA

RD to data valid

(2)

Data is already stable on Port A.

tDVQV–PA

Data in to data out valid

tRHQZ–PA RD to data High-Z

Table 231.

Port A peripheral data mode WRITE timing (5 V PSD module)

Symbol

Parameter

Conditions

Min

Max

Unit

tWLQV–PA WR to data propagation delay

tDVQV–PA

Data to port A data propagation delay

(1)

Data stable on Port 0 pins to data on Port A.

tWHQZ–PA WR Invalid to port a tri-state

Table 232.

Port A peripheral data mode WRITE timing (3 V PSD module)

Symbol

Parameter

Conditions

Min

Max

Unit

tWLQV–PA WR to data propagation delay

tDVQV–PA

Data to port A data propagation delay

(1)

Data stable on Port 0 pins to data on Port A.

tWHQZ–PA WR Invalid to port a tri-state

tDVQV (PA)

tWLQV

(PA)

tWHQZ (PA)

ADDRESS

DATA OUT

A / D BUS

PORT A

DATA OUT

ALE

AI06611

Obsolete

Product(s)

- Obsolete

Product(s)

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