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UPSD3422EB40U6 bảng dữ liệu(PDF) 159 Page - STMicroelectronics

tên linh kiện UPSD3422EB40U6
Giải thích chi tiết về linh kiện  Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic
PDF  300 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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UPSD3422EB40U6 bảng dữ liệu(HTML) 159 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
USB interface
159/300
Figure 54.
FIFO pairing example (1/2 IN paired and 3/4 OUT paired)
25.3.4
Reading and writing FIFOs
There are a total of ten 64-byte FIFOs. Each of the five Endpoints has two FIFOs, one IN
FIFO for IN transactions and one OUT FIFO for OUT transactions. The FIFOs are
accessible by the CPU through a 64-byte segment in the XDATA space when the VISIBLE
Bit is set (see Table 120 on page 170). If the VISIBLE Bit is not set, the FIFOs are not
accessible by the CPU but are still accessible by the SIE. The base address of the 64-byte
segment is specified by the USB base address high register (see Table 130 on page 175)
and the USB base address low register (see Table 132 on page 175). When the VISIBLE Bit
is set, the FIFO that is accessible in the 64-byte XDATA space segment is the FIFO selected
by the USEL register. The USEL register contains two fields used for selecting the
accessible FIFO. The EP field determines the Endpoint selected and the DIR Bit selects the
IN or OUT FIFO associated with the Endpoint.
25.3.5
Accessing FIFO control registers, UCON, and USIZE
Each of the 10 Endpoint FIFOs has an associated USB endpoint control register (UCON,
0F1H) and a USB FIFO valid size register (USIZE, 0F2H). The USB endpoint select register
(USEL) is not only used to select the Endpoint FIFO that is accessible in the XDATA space,
but also selects the associated Endpoint’s UCON and USIZE registers that are accessible at
SFR addresses 0F1H and 0F2H.
8032
MCU
USB SFRs
Serial
interface
engine
CTRL
XDATA
S
F
R
b
u
s
AI10494b
Endpoint4 IN FIFO
Endpoint3 IN FIFO
Endpoint2 IN FIFO
P
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d
P
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d
Endpoint1 IN FIFO
Endpoint0 IN FIFO
Endpoint0 OUT FIFO
Endpoint1 OUT FIFO
Endpoint2 OUT FIFO
FIFO
interface
logic
Endpoint4
Endpoint3
Endpoint2
(not available)
Endpoint2
(not available)
Endpoint1
Endpoint0
Endpoint4
Endpoint3
Endpoint1
Endpoint0
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Endpoint4
(not available)
Endpoint4
(not available)
Endpoint3 OUT FIFO
P
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P
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Endpoint4 OUT FIFO
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Product(s)
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Product(s)



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