UPSD3422EB40U6 datasheet(134/300 Pages) STMICROELECTRONICS

134 / 300 page

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I2C interface

UPSD3422, UPSD3433, UPSD3434, UPSD3454

134/300

Table 88 provides recommended settings for S1SETUP based on various combinations of

fOSC and fSCL. Note that the “Total Sample Period” times in Table 87 on page 134 are

typically slightly less than the minimum Start condition hold time, tHLDSTA for a given I

2C bus

speed.

Important note: The SCL bit rate fSCL must first be determined by bits CR[2:0] in the SFR

S1CON before a value is chosen for SMPL_SET[6:0] in the SFR S1SETUP.

Table 86.

Number of I2C bus samples taken after 1-to-0 transition on SDA (Start

condition)

Contents of S1SETUP

Resulting value for

S1SETUP

Resulting number of

samples taken after 1-to-0

on SDA line

SS_EN bit

SMPL_SET[6:0]

XXXXXXXb

00h (default)

0000000b

80h

0000001b

81h

0000010b

82h

...

0001011b

8Bh

0010111b

97h

...

1111111b

FFh

128

Table 87.

Start condition hold time

I2C bus speed

Range of I2C clock speed

(fSCL)

Minimum Start condition hold

time (tHLDSTA)

Standard

Up to 100 kHz

4000 ns

Fast

101 kHz to 400 kHz

600 ns

High

401 kHz to 833 kHz(1)

833KHz is maximum for UPSD34xx devices.

160 ns

Table 88.

S1SETUP examples for various I2C bus speeds and oscillator

frequencies

I2C bus

speed, fSCL

Parameter

Oscillator frequency, fOSC

6 MHz

12 MHz

24 MHz

33 MHz

40 MHz

Standard

Recommended

S1SETUP value

93h

A7h

CFh

EEh

FFh

Number of samples

111

128

Time between samples

166.6 ns

83.3 ns

41.6 ns

30 ns

25 ns

Total sampled period

3332 ns

3333 ns

3200 ns

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