UPSD3422EB40U6 datasheet(108/300 Pages) STMICROELECTRONICS

108 / 300 page

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Serial UART interfaces

UPSD3422, UPSD3433, UPSD3434, UPSD3454

108/300

21.1.3

Mode 2

Mode 2 provides asynchronous, full-duplex communication using a total of 11 bits per data

byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0');

eight data bits (LSB first); a programmable 9th data bit; and a Stop Bit (logic '1'). Upon

Transmit, the 9th data bit (from bit TB8 in SCON) can be assigned the value of '0' or '1.' Or,

for example, the Parity Bit (P, in the PSW) could be moved into TB8. Upon receive, the 9th

data bit goes into RB8 in SCON, while the Stop Bit is ignored. The baud rate is

programmable to either 1/32 or 1/64 of fOSC.

21.1.4

Mode 3

Mode 3 is the same as Mode 2 in all respects except the baud rate is variable like it is in

Mode 1.

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination

initiated in the other modes by the incoming Start Bit if REN = 1.

21.1.5

Multiprocessor communications

Modes 2 and 3 have a special provision for multiprocessor communications. In these

modes, 9 data bits are received. The 9th one goes into bit RB8, then comes a stop bit. The

port can be programmed such that when the stop bit is received, the UART interrupt will be

activated only if bit RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to

use this feature in multi-processor systems is as follows: When the master processor wants

to transmit a block of data to one of several slaves, it first sends out an address byte which

identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in

an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data

byte. An address byte, however, will interrupt all slaves, so that each slave can examine the

received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and

prepare to receive the data bytes that will be coming. The slaves that were not being

addressed leave their SM2 bits set and go on about their business, ignoring the coming data

bytes.

SM2 has no effect in Mode 0, and in Mode 1, SM2 can be used to check the validity of the

stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless

a valid stop bit is received.

Table 64.

UART operating modes

Mode

Synchronization

Bits of SFR,

SCON

Baud clock

Data

bits

Start/stop

bits

See Figure

SM0

SM1

Synchronous

fOSC/12

None

Figure 30 on

page 113

Asynchronous

Timer 1 or Timer 2

Overflow

1 Start, 1

Stop

Figure 32 on

page 115

Asynchronous

fOSC/32 or fOSC/64

1 Start, 1

Stop

Figure 34 on

page 117

Asynchronous

Timer 1 or Timer 2

Overflow

1 Start, 1

Stop

Figure 36 on

page 118

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