UPSD3422EB40U6 datasheet(102/300 Pages) STMICROELECTRONICS

102 / 300 page

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Standard 8032 timer/counters

UPSD3422, UPSD3433, UPSD3434, UPSD3454

102/300

Note:

The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact

same function as RCLK and TCLK.

4TCLK(1)

R,W

UART0 Transmit Clock control.

When TCLK = 1, UART0 uses Timer 2 overflow pulses for its

transmit clock in Modes 1 and 3. TCLK=0, Timer 1 overflow is

used for transmit clock

EXEN2

R,W

Timer 2 External Enable.

When EXEN2 = 1, capture or reload results when negative

edge on pin T2X occurs. EXEN2 = 0 causes Timer 2 to ignore

events at pin T2X.

TR2

R,W

Timer 2 run control.

1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off.

1C/T2

R,W

Counter or Timer function select.

When C/T2 = 0, function is timer, clocked by internal clock.

When C/T2 = 1, function is counter, clocked by signal sampled

on external pin, T2.

0CP/RL2

R,W

Capture/Reload.

When CP/RL2 = 1, capture occurs on negative transition at pin

T2X if EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs

when Timer 2 overflows, or on negative transition at pin T2X

when EXEN2=1. When RCLK = 1 or TCLK = 1, CP/RL2 is

ignored, and Timer 2 is forced to auto-reload upon Timer 2

overflow

Table 61.

T2CON register bit definition (continued)

Bit

Symbol

R/W

Definition

Table 62.

Timer/counter 2 operating modes

Mode

Bits in T2CON SFR

T2X

(1)

Remarks

Input clock

RCLK

TCLK

CP/

RL2

TR2 EXEN2

Timer,

internal

Counter,

external

(Pin T2,

P1.0)

16-bit

Auto-

reload

reload [RCAP2H, RCAP2L] to

[TH2, TL2] upon overflow

(upcounting)

fOSC/12

MAX

fOSC/24

↓

reload [RCAP2H, RCAP2L] to

[TH2, TL2] at falling edge on pin

T2X

16-bit

capture

16-bit timer/counter

(upcounting)

fOSC/12

MAX

fOSC/24

↓

Capture [TH2, TL2] and store to

[RCAP2H, RCAP2L] at falling

edge on pin T2X

Obsolete

Product(s)

- Obsolete

Product(s)

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