ADV7321 datasheet(18/88 Pages) AD

18 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 18 of 88

Pin No.

Mnemonic

Input/Output

Description

62–58,

55–51

S9 to S0

SD or Progressive Scan/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up

on Pin S0. For 8-bit data input, LSB is set up on S2.

RESET

This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default

47, 35

RSET1, RSET2

A 3040 Ω resistor must be connected from this pin to AGND and is used to control the

amplitudes of the DAC outputs.

SCLK

I2C Port Serial Interface Clock Input.

SDA

I/O

I2C Port Serial Data Input/Output.

ALSB

TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is tied low, the

I2C filter is activated, which reduces noise on the I2C interface.

VDD_IO

Power Supply for Digital Inputs and Outputs.

10, 56

VDD

Digital Power Supply.

VAA

Analog Power Supply.

VREF

I/O

Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

EXT_LF

External Loop Filter for the Internal PLL.

RTC_SCR_TR

Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input.

I2C

This input pin must be tied high (VDD_IO) for the ADV7320/ADV7321 to interface over the I2C port.

GND_IO

Digital Input/Output Ground.

ADV7321 bảng dữ liệu(PDF) 18 Page - Analog Devices

ADV7321 bảng dữ liệu(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

bảng dữ liệu tải về

Link URL