Philips Semiconductors

Product specification

74F373/74F374

Latch/flip-flop

December 5, 1994

4

LOGIC DIAGRAM FOR 74F373

GND = Pin 10

D0

D

E

Q

Q0

3

2

D1

D

E

Q

Q1

4

5

D2

D

E

Q

Q2

7

6

D3

D

E

Q

Q3

8

9

D4

D

E

Q

Q4

13

12

D5

D

E

Q

Q5

14

15

D6

D

E

Q

Q6

17

16

D7

D

E

Q

Q7

18

19

11

1

E

OE

SF00256

LOGIC DIAGRAM FOR 74F374

VCC = Pin 20

D0

D

CP Q

Q0

3

2

D1

D

CP Q

Q1

4

5

D2

D

CP Q

Q2

7

6

D3

D

CP Q

Q3

8

9

D4

D

CP Q

Q4

13

12

D5

D

CP Q

Q5

14

15

D6

D

CP Q

Q6

17

16

D7

D

CP Q

Q7

18

19

11

1

OE

CP

GND = Pin 10

SF00257

FUNCTION TABLE FOR 74F373

INPUTS

INTERNAL

OUTPUTS

OPERATING MODE

OE

E

Dn

REGISTER

Q0 - Q7

OPERATING MODE

L

H

L

L

L

Enable and read register

L

H

H

H

H

Enable and read register

L

↓

l

L

L

Latch and read register

L

↓

h

H

H

Latch and read register

L

L

X

NC

NC

Hold

H

L

X

NC

Z

Disable outputs

H

H

Dn

Dn

Z

Disable outputs

NOTES:

H =

High-voltage level

h

=

High state must be present one setup time before the high-to-low enable transition

L

=

Low-voltage level

l

=

Low state must be present one setup time before the high-to-low enable transition

NC=

No change

X =

Don’t care

Z =

High impedance “off” state

↓ =

High-to-low enable transition