Integrated

Circuit

Systems, Inc.

ICS9214

0809D–04/07/06

Block Diagram

Rambus

TM

XDR

TM

Clock Generator

The ICS9214 clock generator provides the necessary clock

signals to support the Rambus XDR

and Redwood logic interface. The clock source is a reference

clock that may or may not be modulated for spread spectrum.

The ICS9214 provides 4 differential clock pairs in a space

saving 28-pin TSSOP package and provides an off-the-shelf

high-performance interface solution.

Figure 1 shows the major components of the ICS9214 XDR

Clock Generator.

These include the a PLL, a Bypass

Multiplexer and four differential output buffers. The outputs

can be disabled by a logic low on the OE pin. An output is

enabled by the combination of the OE pin being high, and 1

in its SMBus Output control register bit.

The PLL receives a reference clock, CLK_INT/C and outputs

a clock signal at a frequency equal to the input frequency

times a multiplier. Table 2 shows the multipliers selectable

via the SMBus interface. This clock signal is then fed to the

differential output buffers to drive the enabled clocks. Disabled

outputs are set to Hi-Z. The Bypass mode routes the input

clock, CLK_INT/C, directly to the differential output buffers,

bypassing the PLL.

Up to four ICS9214 devices can be cascaded on the same

SMBus. Table 3 shows the SMBus addressing and control for

the four devices.

•

400 – 500 MHz clock source

•

4 open-drain differential output drives with short term

jitter < 40ps

•

Spread spectrum compatible

•

Reference clock is differential or single-ended, 100 or

133 MHz

•

SMBus programmability for:

- frequency multiplier

- output enable

- operating mode

•

Supports frequency multipliers of: 3, 4, 5, 6, 8,

9/2,

15/2 and 15/4

•

Support systems where XDR subsystem is

asynchronous to other system clocks

•

2.5V power supply

PLL

Bypass

MUX

RegA

RegB

RegC

RegD

CLK_INT

CLK_INC

SMBCLK

OE

OE

OE

OE

OE

BYPASS#/PLL

SMBDAT SMB_A0 SMB_A1

ODCLK_C3

ODCLK_T3

ODCLK_C2

ODCLK_T2

ODCLK_C1

ODCLK_T1

ODCLK_C0

ODCLK_T0

AVDD2.5

1

28 VDD2.5

AGND

2

27 ODCLK_T0

IREFY

3

26 ODCLK_C0

AGND

4

25 GND

CLK_INT

5

24 ODCLK_T1

CLK_INC

6

23 ODCLK_C1

VDD2.5

7

22 VDD2.5

GND

8

21 GND

SMBCLK

9

20 ODCLK_T2

SMBDAT 10

19 ODCLK_C2

OE 11

18 GND

SMB_A0 12

17 ODCLK_T3

SMB_A1 13

16 ODCLK_C3

BYPASS#/PLL 14

15 VDD2.5

Pin Configuration

28-Pin 4.4mm TSSOP

General Description

Features