16

Integrated

Circuit

Systems, Inc.

ICS9214

0809D—04/07/06

Revision History

Rev.

Issue Date Description

Page #

Updated SMBus table Byte 2, Bit 3 from:0 to:1.

Updated PLL Multiplier Selection Table, from: Byte 1 to: Byte 0, and Bit 2,1,0,

to: Bit 6,5,4.

Updated Ordering Information from "Lead Free" to "Annealed Lead Free"

A

4/6/2005

Added Phase noise spec

Removed unsupported speeds from PLL Multiplier Selection,

Changed minimum output raise, fall times from 140ps to 100 ps

Compliant with Rev 0.81 of XCG spec.

Various

B

4/22/2005

1. Changed write address from D2 to a valid address (D8)

2. Changed read address from D3 to a valid address (D9)

3

C

11/11/2005 Added the 15/4 entry in the gear table to the list of supported frequencies

5

D

4/7/2006

Added Thermal Characteristics Table.

10

4-5,15

3/30/2005

0.1