AX88780 datasheet(29/49 Pages) ASIX

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AX88780

4.33 TXST--TX Status Register

Offset Address = FC94h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:4

All 0’s

Reserved

TXD3FAIL R

TX Descriptor3 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor3.

This bit will be self-cleared when driver reads TXST register.

TXD2FAIL R

TX Descriptor2 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor2.

This bit will be self-cleared when driver reads TXST register.

TXD1FAIL R

TX Descriptor1 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor1.

This bit will be self-cleared when driver reads TXST register.

TXD0FAIL R

TX Descriptor0 Transmit Fail

When this bit is set 1, it means MAC fails in transmission of descriptor0.

This bit will be self-cleared when driver reads TXST register.

4.34 MDCLKPAT--MDC Clock Pattern Register

Offset Address = FCA0h

Default = 32’h0000_8040

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:8

R/W

8’h80

Reserved, must set to 8’h80 for normal operation

7:0

MDCPAT R/W

8’h40

MDC Clock Divide Factor

This field defines the divide factor of host clock. AX88780 will refer to this

field and generate a low speed clock to PHY.

4.35 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter

Offset Address = FCA4h

Default = 32’h0000_0000

Field Name

Type

Default

Description

31:16

All 0’s Reserved

15:0

RXCHKERCNT R/W

All 0’s RX Checksum Error Counter

If the RXCHKSUM field of RX_CFG register is set to ‘1’, MAC will check

the checksum of IP, TCP or UDP packet. Whenever there is checksum error

detected, this field will be added one.

4.36 RXCRCNT--RX CRC Error Counter

Offset Address = FCA8h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:0

RXCRCCNT R/W

All 0’s

RX CRC32 Error Counter

MAC checks the received packet. If there is a CRC error detect, this field

will be added one.

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