AX88780 datasheet(22/49 Pages) ASIX

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AX88780

transmitted.

4.11 TXDES3--TX Descriptor3 Register

Address = FC2Ch

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

TXD3_EN

R/W

Transmit TX descriptor3

If this bit is enabled, MAC will begin to transmit data that are stored in TX

buffer. In former, data had been written to TX descriptor3. This bit will be

cleared by hardware when MAC finished the transmission.

1= enable

0= disable

14:13

2’b00

Reserved

12:0

TXD3_LEN

R/W

All 0’s

TX Packet Length (unit: byte)

Driver set this field to indicate AX88780 how many bytes will be

transmitted.

4.12 RX_CFG--RX Configuration Register

Offset Address = FC30h

Default = 32’h0000_0100

Field

Name

Type

Default

Description

31:9

All 0’s

Reserved

RXFLOW

R/W

RX Flow Control

To enable RX flow control, driver MUST set this bit and bit5 of

MAC_CFG1.

1 = enable

0 = disable

7:5

R/W

3’b000

Reserved.

RXCHKSUM

R/W

RX Packet TCP/IP Checksum

When this bit is set, AX88780 will check the checksum of the received

packet that is IP, TCP or UDP packet. If there is checksum error, AX88780

will drop the packet and RXCHKSUMCNT counter will add 1.

1 = enable

0 = disable

3:1

R/W

3’b000

Reserved

RXBUFPRO

R/W

RX Buffer Protection

When this bit is enabled, MAC will protect the RX buffer to avoid overrun.

For normal operation, this bit should be enabled in initial stage.

1= enable

0= disable

4.13 RXCURT--RX Current Pointer Register

Offset Address = FC34h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:11

All 0’s

Reserved

10:0

RXCURPTR

R/W

All 0’s

RX Line Current Pointer.

Point to the last line that will be written by hardware. The unit of line is 16

bytes. MAC will maintain this register.

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