CY25562
Document #: 38-07392 Rev. *B
Page 3 of 8
Tri-level Logic
With binary logic, four states can be programmed with two
control lines, whereas tri-level logic can program nine logic
states using two control lines. Tri-level logic in the CY25562 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0.” Pins 6 and 7 of the CY25562
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
“1” (One). Each of these states have a defined voltage range
that is interpreted by the CY25562 as “0”, “M,” or “1” logic state.
Refer to Table 2 for voltage ranges for each logic state. The
CY25562 has two equal value resistors connected internally
to pin 6 and pin 7, which produce the default “M” state. Pins 6
and/or 7 can be tied directly to ground or VDD to program a
logic “0” or “1” state, respectively. See examples below.
SSCG Theory of Operation
The CY25562 is a PLL-type clock generator using a propri-
etary Cypress design to modulate the reference clock.
By
precisely controlling the bandwidth of the output clock, the
CY25562 becomes a low-EMI clock generator. The theory and
detailed operation of the CY25562 will be discussed in the
following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50-duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI use shielding, filtering, multi-layer
PCBs, etc. The CY25562 reduces the peak energy in the clock
by increasing the clock bandwidth, thus lowering the Q.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
Table 1. Frequency and Spread % Selection (Center Spread)
50 – 100 M H z ( L ow R a n g e)
In p u t
F r e q ue nc y
(M H z )
S1 = M
S0 = M
(% )
S1 = M
S0 = 0
(% )
S1 = 1
S0 = 0
(% )
S1 = 0
S0 = 0
(% )
S1 = 0
S0 = M
(% )
50 - 60
4 . 3
3 . 9
3. 3
2. 9
2. 7
60 - 70
4 . 0
3 . 6
3. 1
2. 6
2. 5
70 - 80
3 . 8
3 . 4
2. 9
2. 5
2. 4
80 - 100
3 . 5
3 . 1
2. 7
2. 2
2. 1
10 0 – 200 M H z ( H i g h R a n g e)
In p u t
F r e q ue nc y
(M H z )
S1 = 1
S0 = M
(% )
S1 = 0
S0 = 1
(% )
S1 = 1
S0 = 1
(% )
S1 = M
S0 = 1
(% )
10 0 – 120
3 . 0
2 . 4
1. 6
1. 3
120 - 130
2 . 7
2 . 1
1. 4
1. 1
1 30 - 1 4 0
2 . 6
2 . 0
1. 3
1. 1
1 40 - 1 5 0
2 . 6
2 . 0
1. 3
1. 1
1 50 - 1 6 0
2 . 5
1 . 8
1. 2
1. 0
1 60 - 1 7 0
2 . 4
1 . 8
1. 2
1. 0
1 70 - 1 8 0
2 . 4
1 . 8
1. 2
1. 0
1 80 - 1 9 0
2 . 3
1 . 7
1. 1
0. 9
1 90 - 2 0 0
2 . 3
1 . 6
1. 1
0. 9
S e l ect t h e
Fr e que n c y a nd
C e n t er S p r ead %
de s i r e d a nd t h e n
set S 1 , S 0 as
i ndi c a t e d.
S e l ect t h e
Fr e que n c y a nd
C e n t er S p r ead %
de s i r e d a nd t h e n
set S 1 , S 0 as
i ndi c a t e d.
CY25562
CY25562
CY25562
7
6
5
VDD
S0 = "M" (N/C)
S1 = "0" (GND)
7
7
6
6
5
5
VDD
VDD
VDD
S0
S1
S0
S0
S1
S1
SSCC = "1"
SSCC = "1"
S1 = "0" (GND)
S0 = "1"
S0 = "1"
S1 = "1"
SSCC = "1"
Figure 1. Tri-level Logic Examples
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