CY25562
Document #: 38-07392 Rev. *B
Page 4 of 8
both peak and cycle to cycle. The CY25562 takes a narrow
band digital reference clock in the range of 50–200 MHz and
produces a clock that sweeps between a controlled start (F1)
and stop (F2) frequency at a precise rate of change. To under-
stand what happens to a clock when SSCG is applied,
consider a 200 MHz clock with a 50 % duty cycle. From a
200-MHz clock we know the following:
Clock Frequency = fc = 200 MHz
Clock Period = Tc = 1/200 MHz.
If this clock is applied to the Xin/CLK pin of the CY25562, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition, sweep, from F1 to F2, the amount of time and
sweep waveform become a very important factor in the
amount of EMI reduction realized from an SSCG clock.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. Figure 2 shows the
modulation profile of a 200-MHz SSCG clock. Notice that the
actual sweep waveform is not a simple sine or sawtooth
waveform. Figure 2 also shows a scan of the same SSCG
clock using a spectrum analyzer. The spectrum analyzer scan
shows a 10-dB reduction in the peak RF energy when using
the CY25562 SSCG clock.
Modulation Rate
Spread
Spectrum
clock
generators
utilize
frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmod.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The CY25562 has a fixed
divider count of 2332.
Tc = 5.0 ns
50 %
50 %
Device
Cdiv
CY25562
2332
(All Ranges)
Example:
Device =
CY25562
Fin
=
200 MHz
Range =
S1 = 1, S0 = 1
Then;
Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.
Modulation Profile
Spectrum Analyzer
Figure 2. SSCG Clock, CY25562, Fin = 200 MHz
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