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CY25562
Document #: 38-07392 Rev. *B
Page 5 of 8
CY25562 Application Schematic
The schematic in Figure 3 above demonstrates how the
CY25562 is configured in a typical application. This application
is using a 200-MHz reference clock connected to pin 1.
Because an external reference clock is used, pin 8 (Xout) is
left unconnected.
This configuration depicts the profile and spectrum scans
shown in Figure 2. Note that S0 = S1 = 1, for a spread of
approximately 1.1%.
VDD
1
8
SSCC
VSS
S1
S0
XIN/CLK
XOUT
SSCLK
VDD
CY25562
5
7
6
4
0.1 uF
C3
2
3
VDD
200 MHz Reference Clock
VDD
Figure 3. Application Schematic
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