MPC8540 datasheet(245/1302 Pages) FREESCALE

245 / 1302 page

Legacy Support of PowerPC Architecture

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-31

5.13 Legacy Support of PowerPC Architecture

This section provides an overview of the architectural differences and compatibilities of the e500

core compared with the AIM PowerPC architecture. The two levels of the e500 programming

environment are as follows:

•

User level—This defines the base user-level instruction set, user-level registers, data types,

memory conventions, and the memory and programming models seen by application

programmers.

•

Supervisor level—This defines supervisor-level resources typically required by an

operating system, the memory management model, supervisor level registers, and the

exception model.

In general, the e500 core supports the user-level architecture from the existing AIM architecture.

The following subsections are intended to highlight the main differences. For specific

implementation details refer to the relevant chapter.

5.13.1 Instruction Set Compatibility

The following sections generally describe the user and supervisor instruction sets.

5.13.1.1 User Instruction Set

The e500 core executes legacy user-mode binaries and object files except for the following:

•

The e500 supports vector and scalar single-precision floating-point operations as APUs.

These instructions have different encoding than the AIM definition of the PowerPC

architecture. Additionally, the e500 core uses GPRs for floating-point operations, rather

than the FPRs defined by the UISA. Most porting of floating-point operations can be

handled by recompiling.

•

String instructions are not implemented on the e500; therefore, trap emulation must be

provided to ensure backward compatibility.

5.13.1.2 Supervisor Instruction Set

The supervisor mode instruction set defined by the AIM version of the PowerPC architecture is

compatible with the e500 with the following exceptions:

•

The MMU architecture is different, so some TLB manipulation instructions have different

semantics.

•

Instructions that support the BATs and segment registers are not implemented.

MPC8540 bảng dữ liệu(PDF) 245 Page - Freescale Semiconductor, Inc