MPC8540 datasheet(242/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-28

Freescale Semiconductor

Core Complex Overview

instruction is also broadcast on the core complex bus (CCB) if HID1[ABE] is set. The core

complex also snoops TLB invalidate transactions on the CCB from other bus masters.

On the MPC8540 the ABE bit must be set to ensure that cache and TLB management instructions

operate properly on the L2 cache.

5.10 Memory Coherency

The core complex supports both three- and four-state memory coherency. Memory coherency is

hardware-supported on the system bus through bus snooping and the retry/copyback bus protocol,

and through broadcasting of cache management instructions. Translation coherency is also

hardware-supported through broadcasting and bus snooping of TLB invalidate transactions. The

four-state MESI protocol supports efficient large-scale real-time data sharing between multiple

caching bus masters.

5.10.1 Atomic Update Memory References

The e500 core supports atomic update memory references for both aligned word forms of data

using the load and reserve and store conditional instruction pair, lwarx and stwcx.. Typically, a

load and reserve instruction establishes a reservation and is paired with a store conditional

instruction to achieve the atomic operation. However, there are restrictions and requirements for

this functionality. Because the processor revokes reservations during context switches, the

programmer must reacquire the reservation after a context switch to maintain reservations across

context switches.

5.10.2 Memory Access Ordering

The core complex supports weakly ordered references to memory. Thus the e500 manages the

order and synchronization of instructions to ensure proper execution when memory is shared

between multiple processes or programs. The cache and data memory control attributes along with

msync and mbar provide the required access control.

5.10.3 Cache Control Instructions

The core complex supports Book E instructions for performing a full range of cache control

functions, including cache locking by line. The core complex supports broadcasting and snooping

of these cache control instructions on the CCB. The e500 core also supports the following

e500-specific cache locking instructions:

•

Data Cache Block Lock Clear (dcblc)

•

Data Cache Block Touch-and-Lock Set (dcbtls)

•

Data Cache Block Touch for Store and Lock Set (dcbtstls)

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