MPC8540 datasheet(241/1302 Pages) FREESCALE

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Memory Management

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-27

5.9.2

MMU Assist Registers (MAS1–MAS4 and MAS6)

Book E defines SPR numbers for the MMU assist registers, which are used to hold values either

read from or to be written to the TLBs and information required to identify the TLB to be accessed.

To ensure consistency among Freescale Semiconductor Book E processors, certain aspects of the

implementation are defined by the Freescale Semiconductor Book E standard, whereas more

specific details are left to individual implementations. MAS3 implements the real page number

(RPN), the user attribute bits (U0–U3), and permission bits (UX, SX, UW, SW, UR, SR) that

specify user and supervisor read, write, and execute permissions.

The e500 does not implement MAS5.

MAS registers are affected by the following instructions:

•

MAS registers are accessed with the mtspr and mfspr instructions.

•

The TLB Read Entry instruction (tlbre) causes the contents of a single TLB entry from the

L2 MMU to be placed in defined locations in MAS0–MAS3. The TLB entry to be extracted

is determined by information written to MAS0 and MAS2 before the tlbre instruction is

executed.

•

The TLB Write Entry instruction (tlbwe) causes the information stored in certain locations

of MAS0–MAS3 to be written to the TLB specified in MAS0.

•

The TLB Search Indexed instruction (tlbsx) updates MAS registers conditionally, based on

success or failure of a lookup in the L2 MMU. The lookup is specified by the instruction

encoding and specific search fields in MAS6. The values placed in the MAS registers may

differ, depending on a successful or unsuccessful search.

For TLB miss and certain MMU-related DSI/ISI exceptions, MAS4 provides default values for

updating MAS0–MAS2.

5.9.3

Process ID Registers (PID0–PID2)

The e500 core complex also implements three process ID (PID) registers that hold the values used

to construct the three virtual addresses for each access. These process IDs provide an extended

page sharing capability. Which of these three virtual addresses is used is controlled by the TID

field of a matching TLB entry, and when TID = 0x00 (identifying a page as globally shared), the

PID values are ignored.

A hit to multiple TLB entries in the L1 MMU (even if they are in separate arrays) or a hit to

multiple entries in the L2 MMU is considered to be a programming error.

5.9.4

TLB Coherency

The core complex provides the ability to invalidate a TLB entry as defined in the Book E

architecture. The tlbivax instruction invalidates a matching local TLB entry. Execution of this

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