STW81101ATR datasheet(21/42 Pages) STMICROELECTRONICS

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STW81101

I2C bus interface

21/42

I2C bus interface

The I2C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V.

Data transmission from microprocessor to the STW81101 takes place through the 2 wires

(SDA and SCL) I2C-BUS interface. The STW81101 is always a slave device.

The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and

any device that reads the data as receiver. The device that controls the data transfer is

known as the Master and the others as the slave. The master will always initiate the transfer

and will provide the serial clock for synchronization.

5.1

General features

5.1.1

Power ON reset

The device at Power ON is able to configure itself to a fixed configuration, with all

programmable bits set to factory default setting.

5.1.2

Data validity

Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while

the clock is HIGH are used to identify START or STOP condition.

Figure 16.

Data validity

5.1.3

START condition

A Start condition is identified by a HIGH to LOW transition of the data bus SDA while the

clock signal SCL is stable in the HIGH state. A Start condition must precede any command

for data transfer.

5.1.4

STOP condition

A LOW to HIGH transition of the data bus SDA identifies stop while the clock signal SCL is

stable in the HIGH state. A STOP condition terminates communications between the

STW81101 and the Bus Master.

SDA

SCL

CHANGE

DATA

ALLOWED

DATA LINE

STABLE DATA

VALID

SDA

SCL

CHANGE

DATA

ALLOWED

DATA LINE

STABLE DATA

VALID

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