STW81101ATR datasheet(16/42 Pages) STMICROELECTRONICS

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General description

STW81101

16/42

General description

The block diagram of Figure 1 shows the different blocks, which have been integrated to

achieve an integer-N PLL frequency synthesizer.

The STW81101 consists of 2 internal low-noise VCOs with buffer blocks, a divider by 2, a

divider by 4, a low-noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit

programmable reference divider, two programmable counters and a programmable dual-

modulus prescaler. The A-counter (5 bits) and B counter (12 bits) counters, in conjunction

with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider,

where N = B*P +A. The division ratio of both reference and VCO dividers is controlled

through the selected digital interface (I2C bus or SPI).

The selection of the digital interface type is done by the proper hardware connection of the

pin DBUS_SEL (0 V for I2C bus, 3.3 V for SPI).

All devices operate with a power supply of 3.3 V and can be powered down when not in use.

4.1

Circuit description

4.1.1

Reference input stage

The reference input stage is shown in Figure 11. The resistor network feeds a DC bias at the

Fref input while the inverter used as the frequency reference buffer is AC coupled.

Figure 11.

Reference Frequency Input Buffer

4.1.2

Reference divider

The 10-bit programmable reference counter allows the input reference frequency to be

divided to produce the input clock to the PFD. The division ratio is programmed through the

digital interface.

4.1.3

Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it

down to a manageable frequency for the CMOS A and B counters. The modulus (P) is

programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which

division ratio depends on the state of the modulus input.

INV

BUF

VDD

Fref

Power Down

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