STW81101ATR datasheet(13/42 Pages) STMICROELECTRONICS

13 / 42 page

STW81101

Electrical specifications

13/42

Upon request an Evaluation Kit is available including a powerful simulation tool

(STWPLLSim) which allows to estimate very accurately the Phase Noise of the device

according to the desired project parameters (VCO Frequency, Selected Output Stage,

Reference Clock, Frequency Step, …); refer to the Application Information (Section 7) for

more details.

Phase Noise @ 10 MHz

-150

dBc/Hz

Phase Noise @ 20 MHz

-152

dBc/Hz

Phase Noise Floor @ 40 MHz

-154

dBc/Hz

VCO B with divider by 2 (1900MHz-2200MHz) – Open Loop(3)

Phase Noise @ 1 KHz

-61

dBc/Hz

Phase Noise @ 10 KHz

-88

dBc/Hz

Phase Noise @ 100 KHz

-110

dBc/Hz

Phase Noise @ 1 MHz

-133

dBc/Hz

Phase Noise @ 10 MHz

-150

dBc/Hz

Phase Noise @ 20 MHz

-152

dBc/Hz

Phase Noise Floor @ 40 MHz

-154

dBc/Hz

VCO A with divider by 4 (825MHz-975MHz) – Open Loop(3)

Phase Noise @ 1 KHz

-68

dBc/Hz

Phase Noise @ 10 KHz

-95

dBc/Hz

Phase Noise @ 100 KHz

-117

dBc/Hz

Phase Noise @ 1 MHz

-139

dBc/Hz

Phase Noise @ 10 MHz

-151

dBc/Hz

Phase Noise Floor @ 40 MHz

-154

dBc/Hz

VCO B with divider by 4 (950MHz-1100MHz) – Open Loop(3)

Phase Noise @ 1 KHz

-67

dBc/Hz

Phase Noise @ 10 KHz

-94

dBc/Hz

Phase Noise @ 100 KHz

-116

dBc/Hz

Phase Noise @ 1 MHz

-138

dBc/Hz

Phase Noise @ 10 MHz

-151

dBc/Hz

Phase Noise Floor @ 40 MHz

-154

dBc/Hz

Phase Noise SSB.

VCO amplitude setting to value [10].

All the closed-loop performances are specified using a Reference Clock signal at 76.8 MHz with phase noise of

-135dBc/Hz @1KHz offset, -145dBc/Hz @10KHz offset and -149.5dBc/Hz of noise floor.

Normalized PN = Measured PN – 20log(N) – 10log(fPFD) where N is the VCO divider ratio (N=B*P+A) and fPFD is the

comparison frequency at the PFD input

Typical Phase Noise at centre band frequency

Table 6.

Phase noise specification (continued)

Parameter

Test conditions

Min

Typ

Max

Unit

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