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L9374TRLF bảng dữ liệu(PDF) 28 Page - STMicroelectronics |
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L9374TRLF bảng dữ liệu(HTML) 28 Page - STMicroelectronics |
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28 / 80 page ![]() Circuit description L9374LF 28/80 DocID025414 Rev 1 Figure 14. Synchronization controller block diagram Inputs The synchronization controller receives the following input signals: f_A = 4 kHz for internal clocking. SYNC_TRIG =”1” initiates the synchronization timing with that SPI event. SPI synchronization values (SYNC_VALUE, RESET_VALUE, STW_V_MIN; STW_V_MAX) provide the parameters that allow for output synchronization. Outputs The synchronization controller provides the following output signals: The STW signal is used in conjunction with accessing address 0 to notify the master that the SPI cycles are within the programmed exclusionary window (SYNC_F=1). The SYNC_SIG initiates the actuation of the new output commands. The synchronization counter increases its value with every period of f_A. When the value of the counter equals the SYNC_VALUE a synchronization signal (SYNC_SIG) is generated (SYNC_SIG=’1’). The synchronization counter continually counts to the RESET_VALUE and resets unless a SYNC_TRIG command is sent. If a SYNC_TRIG command is sent then the counter resets immediately. Upon resetting the SYNC_TRIG and STW signals are reset (SYNC_SIG = STW =’0’). |
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