L9374TRLF datasheet(58/80 Pages) STMICROELECTRONICS

58 / 80 page

Programmers guide

L9374LF

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5.1.2

Sync tolerance window (STW) register (address 1)

STW value:

These two sets of 5 bits each define a window (between min and max) where accessing

address ‘0’ within this window will cause a sync failure indication (SYNC_F).

To keep the resolution meaningful for the entire range of Sync Triggering the resolution is

dependant on the RESET_VALUE MSB. For programming the two values to the STW the

master has to write both values (2 x 5 bit).

For this section see Chapter 4.3: Synchronization controller for more details

5.1.3

Configuration register 1 (address 2)

Silent valve driver test (SVDT):

These two bits (D0 & D1) are normally set to ‘01’. Writing '10' to these two bits starts the

silent valve driver test.

(for more details see Chapter 4.8.13: Silent valve driver test (SVDT))

MSB

LSB

00010

STW_V_MAX

STW_V_MIN

Parit

free

Table 41. STW value

STW value

Name

Bit

location

Number

of bits

bit time

RESET_VALUE

≤ 0111(2)

bit time

RESET_VALUE

≥ 1000(2)

STW value min.

STW_V_MIN

D0 - D4

250

μs

500

μs

STW value max.

STW_V_MAX

D5 - D9

250

μs

500

μs

MSB

LSB

EDGE_SH

FSON_

FSOFF_ALL

CLKIN_S

SVDT

Parity

free

Table 42. Configuration register 1

Config register

Name

Bit location

Number of bits

Silent valve driver test

SVDT

D0 - D1

2 Bit

CLKIN frequency 1MHz / 250kHz

CLKIN_S

D2 - D3

2 Bit

Fast switch off all

FSOFF_ALL

D4 - D5

2 Bit

Fast switch on enable (general)

FSON_EN

1 Bit

Edge shaping on / off

EDGE_SH

D7 - D8

2 Bit

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