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L9374TRLF bảng dữ liệu(PDF) 54 Page - STMicroelectronics |
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L9374TRLF bảng dữ liệu(HTML) 54 Page - STMicroelectronics |
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54 / 80 page ![]() Circuit description L9374LF 54/80 DocID025414 Rev 1 The SVDT test examples Figure 35. Test failed: short circuit / overload A failed test sequence for overload condition: 1. Disable Edge Shaping (Command address 2, bits D8 & D7 = ‘10’) 2. Initiate SVDT (Command address 2; bits D1 & D0 = ‘10’) 3. Qx switches on at the next sync-signal (sequence of actuation: Q1..Q4) 4. The output current increases and reached IOL before tx is reached 5. Output Qx is switched off for overload protection and the overload bit (bit D0 of the status registers D1 - D4). 6. After the output is disabled if the output clamps the voltage to VZ (35V) a Dx_Loss is detected. 7. If an Over temperature is not detected then the SDVT test is passed 8. The SVDT will then test at Qx+1 until all 4 outputs have been tested. Criterion: The output current increases and reaches overcurrent value within the test time tx SPI: Status registers 1 - 4, OL_Qx bit is set. |
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