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AM6421 bảng dữ liệu(PDF) 80 Page - Texas Instruments

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tên linh kiện AM6421
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AM6421 bảng dữ liệu(HTML) 80 Page - Texas Instruments

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Table 6-58. Power Supply Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
VDDA_TEMP1
PWR
TEMP1 analog supply
L11
VDDR_CORE
PWR
RAM supply
L10, M13
VDDSHV0
PWR
IO supply for IO group 0
F11, G12, G14
VDDSHV1
PWR
IO supply for IO group 1
M7, N6, P7
VDDSHV2
PWR
IO supply for IO group 2
R10, R8, T9
VDDSHV3
PWR
IO supply for IO group 3
P14, P15
VDDSHV4
PWR
IO supply for IO group 4
M14, M15
VDDSHV5
PWR
IO supply for IO group 5
L14, L15
VDDSHV_MCU
PWR
IO supply for IO MCU
F9, G10, G8
VDDS_DDR
PWR
DDR PHY IO supply
F7, G6, H7, J6,
K7, L6
VDDS_DDR_C
PWR
DDR clock IO supply
J8
VDDS_MMC0
PWR
MMC0 PHY IO supply
K14
VDDS_OSC
PWR
MCU_OSC0 supply
H13
VDD_CORE
PWR
Core supply
J10, J12, K11,
K9, L12, L8,
M11, M9, N10,
N8, P9
VDD_DLL_MMC0
PWR
MMC0 PLL analog supply
H14
VDD_MMC0
PWR
MMC0 PHY core supply
K13
VPP
PWR
eFuse ROM programming supply
G15
VSS
GND
Ground
A1, A21, A5, A6,
AA1, AA15,
AA18, AA21,
C10, C15, C3,
D1, E11, E13,
F10, F15, F8,
G1, G16, G3,
G7, G9, H11,
H20, H21, H6,
H8, J14, J7, J9,
K6, K8, L1, L16,
L3, L7, L9, M10,
M12, M6, M8,
N11, N13, N15,
N7, N9, P1, P10,
P18, P6, P8,
R12, R7, R9,
T10, T11, T15,
T16, T8, U3,
V17, W10, W18,
Y14, Y17, Y19
(1)
This pin must always be connected via a 1-μF capacitor to VSS.
(2)
This pin must always be connected via a 3.3-μF ±20% capacitor to VSS.
6.3.19 PRU_ICSSG
Note
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU
GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in
the device TRM.
AM6442, AM6441, AM6422, AM6421, AM6412, AM6411
SPRSP56E – JANUARY 2021 – REVISED SEPTEMBER 2022
www.ti.com
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Product Folder Links: AM6442 AM6441 AM6422 AM6421 AM6412 AM6411



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