RHFLVDSR2D2 datasheet(8/17 Pages) STMICROELECTRONICS

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Electrical characteristics

RHFLVDSR2D2

8/17

DocID025372 Rev 3

Cold sparing

The RHFLVDSR2D2 features a cold spare input and output buffer. In high reliability

applications, cold sparing enables a redundant device to be tied to the data bus with its

power supply at 0 V (VCC = GND) without affecting the bus signals or injecting current from

the I/Os to the power supplies. Cold sparing also allows redundant devices to be kept

powered off so that they can be switched on only when required. This has no impact on the

application. Cold sparing is achieved by implementing a high impedance between the I/Os

and VCC. ESD protection is ensured through a non-conventional dedicated structure.

Fail-safe

In many applications, inputs need a fail-safe function to avoid an uncertain output state

when the inputs are not connected properly. For the drivers: in case of an LVDS input short

circuit or floating inputs, the TTL outputs remain in stable logic-high state.

tPHLD

Propagation delay time, high to

low output

VID = 200 mVp-p, input pulse

from 1.1 V to 1.3 V, VCM = 1.2 V

Load: refer to Figure 6

12.5

tPLHD

Propagation delay time, low to

high output

12.5

tSK1

Channel-to-channel skew(2)

VID = 200 mVp-p

Load: refer to Figure 3

0.25

tSK2

Chip-to-chip skew(3)(4)

0.7

tSKD

Differential skew(5)



(tPHLD-tPLHD)

0.3

t r

Output signal rise time

Load: refer to Figure 3

0.9

t f

Output signal fall time

0.9

tPLZ

Propagation delay time, low

level to high impedance output

Load: refer to Figure 4

3.8

tPHZ

Propagation delay time, high

level to high impedance output

3.8

tPZH

Propagation delay time, high

impedance to high level output

3.8

tPZL

Propagation delay time, high

impedance to low level output

3.8

tD1

Fail-safe to active time

µs

tD2

Active to fail-safe time

1. All pins except pin under test and VCC are floating

2. tSK1 is the maximum delay time difference between all outputs of the same device (measured with all inputs connected

together).

3. tSK2 is the maximum delay time difference between outputs of all devices when they operate with the same supply voltage,

at the same temperature.

4. Guaranteed by design

5. tSKD is the maximum delay time difference between tPHLD and tPLHD, see Figure 3.

6. Guaranteed by characterization on bench.

Table 7. Electrical characteristics (continued)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

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