UCC28C53_V01 datasheet(20/48 Pages) TI

20 / 48 page

VREF

COMP

2N2907

To VOUT

Figure 8-6. Soft-Start Implementation

The limited charging current of the amplifier into the capacitor translates into a dv/dt limitation on the error

amplifier output. This directly corresponds to some maximum rate of change of primary current in a current mode

controlled system as one of the PWM comparator inputs gradually rises. The values of RSS and CSS must be

selected to bring the COMP pin up at a controlled rate, limiting the peak current supplied by the power stage.

After the soft-start interval is complete, the capacitor continues to charge to VREF, effectively removing the PNP

transistor from the circuit consideration. Soft-start timing offers a different, frequently preferred function in current

mode controlled systems than it does in voltage mode control. In current mode, soft start controls the rising of

the peak switch current. In voltage mode control, soft start gradually widens the duty cycle, regardless of the

primary current or rate of ramp-up.

The purpose of resistor RSS and the diode is to remove the soft-start capacitor from the error amplifier path

during normal operation, after the soft-start period completes and the capacitor charges fully. The optional

diode in parallel with the resistor forces a soft-start period each time the PWM goes through UVLO condition

that forces VREF to go low. Without the diode, the capacitor remains charged during a brief loss of supply or

brown-out, and the device does not emable a soft-start function upon re-application of VDD.

8.3.8 Enable and Disable

There are several ways to enable or disable the UCCx8C5x devices, depending on which type of restart is

required. The two basic techniques use external transistors to either pull the error amplifier output low (< 2 VBE)

or pull the current sense input high (> 1.1 V). Application of the disable signal causes the output of the PWM

comparator to be high. The PWM latch is reset dominant so that the output remains low until the next clock

cycle after the shutdown condition at the COMP or CS pin is removed. Another choice for restart without a

soft-start period is to pull the current sense input above the cycle-by-cycle current limiting threshold. A logic level

P-channel FET from the reference voltage to the current sense input can be used.

COMP

DISABLE

Figure 8-7. Disable Circuit

8.3.9 Slope Compensation

With current mode control, slope compensation is required to stabilize the overall loop with duty cycles

exceeding 50%. Although not required, slope compensation also improves stability in applications using below

a 50% maximum duty cycle. Slope compensation is introduced by injecting a portion of the oscillator waveform

to the actual sensed primary current. The two signals are summed together at the current sense input (CS)

connection at the filter capacitor. To minimize loading on the oscillator, it is best to buffer the timing capacitor

waveform with a small transistor whose collector is connected to the reference voltage.

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

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