UCC28C53_V01 datasheet(4/48 Pages) TI

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6 Pin Configuration and Functions

COMP

VREF

VDD

OUT

RT/CT

GND

Not to scale

Figure 6-1. D Package 8-Pin SOIC (Top View)

COMP

VREF

VDD

OUT

RT/CT

GND

Not to scale

Figure 6-2. DGK Package, 8-Pin VSSOP 9 (Top

View)

Table 6-1. Pin Functions

TYPE

(1)

DESCRIPTION

NAME

NO.

COMP

This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently

used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the

secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited

so the user can command zero duty cycle by externally forcing COMP to GND.

Primary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator.

Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier

output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to

this pin to run the device with a voltage mode control configuration.

This pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback

loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ± 1%.

GND

—

Ground return pin for the output driver stage and the logic level controller section.

OUT

The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the

UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 is the same frequency as the oscillator,

and can operate near 100% duty cycle. In the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and

UCC28C59, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the

maximum duty cycle to < 50%. Peak currents of up to 1 A are sourced and sunk by this pin. OUT is actively

held low when VDD is below the turn-on threshold.

RT/CT

I/O

Fixed frequency oscillator set point. Connect timing resistor (RRT) to VREF and timing capacitor (CCT) to GND

from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device

GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and

all other functions. The switching frequency (fSW) of the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L

and UCC28C58 gate drive is equal to fOSC; the switching frequency of the UCCx8C51, UCCx8C54, and

UCCx8C55, UCC28C57H/L and UCC28C59 is equal to half of the fOSC.

VDD

Analog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent

VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND

with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate

capacitance of the main switching FET used in the design and at least 10 times greater than the capacitance

on the VREF pin used in the design are also required on VDD.

VREF

5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the

timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor

connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF

bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed

to superimposed to VREF pin since VREF is an ouput.

(1)

I = input, O = output, G = ground

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

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