XGS datasheet(36/53 Pages) ONSEMI

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XGS Family

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FOUR−WIRE SERIAL INTERFACE

The sensor’s configuration registers are accessible

through a Four−Wire or Serial Peripheral Interface (SPI).

The SPI is a full−duplex, synchronous interface and uses

four wires:

• CS_N: Chip Select (active low)

• SCLK: Serial Input Clock

• SDATA: Serial Data Input

• SDATAOUT: Serial Data Output

The SPI interface uses a master−slave setup in which the

sensor is the slave. Every read or write access is initiated by

the master by pulling down the CS_N line. The master then

sends a 15−bit register address followed by a single

read/write bit. If the read/write bit is set to 1, the slave reads

the 16−bit data stored at the specified register address and

returns it to the master over the SDATAOUT line. A single SPI

read operation is shown in Figure 45. In case the read/write

bit is set to ‘0’, the master sends another 16 bits of data for

the slave to write to the previously specified register address.

A single SPI write transaction is depicted in Figure 46.

Both address and register data is sent serially and

synchronous to the SCLK. A single SPI transaction consists

of 32 bits. In order to speed up the SPI communication, a

32 sequential read and write is possible. The sequential

Figure 45. Single SPI Read

Figure 46. SPI Single Write

Figure 47. SPI Sequential Read

Figure 48. SPI Sequential Write

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