PIC16F616-ESLASHMLQTP datasheet(17/172 Pages) APEX

17 / 172 page

Preliminary

DS41288A-page 15

PIC16F616/16HV616

2.2.2.5

PIR1 Register

The PIR1 register contains the peripheral interrupt flag

bits, as shown in Register 2-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register. User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0

R/W-0

U-0

R/W-0

—

ADIF

CCP1IF

C2IF

C1IF

—

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

ADIF: A/D Interrupt Flag bit

= A/D conversion complete

= A/D conversion has not completed or has not been started

bit 5

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 4

C2IF: Comparator C2 Interrupt Flag bit

= Comparator C2 output has changed (must be cleared in software)

= Comparator C2 output has not changed

bit 3

C1IF: Comparator C1 Interrupt Flag bit

= Comparator C1 output has changed (must be cleared in software)

= Comparator C1 output has not changed

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

= Timer2 to PR2 match occurred (must be cleared in software)

= Timer2 to PR2 match has not occurred

bit 0

TMR1IF: Timer1 Overflow Interrupt Flag bit

= Timer1 register overflowed (must be cleared in software)

= Timer1 has not overflowed

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