PIC16F616-ESLASHML datasheet(112/172 Pages) APEX

112 / 172 page

PIC16F616/16HV616

DS41288A-page 110

Preliminary

11.6

Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator, which requires no external components. This

RC oscillator is separate from the external RC oscillator

of the CLKIN pin and INTOSC. That means that the

WDT will run, even if the clock on the OSC1 and OSC2

pins of the device has been stopped (for example, by

execution of a SLEEP instruction). During normal oper-

ation, a WDT time out generates a device Reset. If the

device is in Sleep mode, a WDT time out causes the

device to wake-up and continue with normal operation.

The WDT can be permanently disabled by program-

ming

the

Configuration

bit,

WDTE,

clear

(Section 11.1 “Configuration Bits”).

11.6.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms (with

prescaler).

The

time-out

periods

vary

with

temperature, VDD and process variations from part to

part (see DC specs). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control by

writing to the OPTION register. Thus, time-out periods

up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the prescaler, if assigned to the WDT, and prevent

it from timing out and generating a device Reset.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time out.

11.6.2

WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst case

conditions (i.e., VDD = Min., Temperature = Max., Max.

WDT prescaler) it may take several seconds before a

WDT time out occurs.

FIGURE 11-2:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 11-7:

WDT STATUS

Conditions

WDT

WDTE = 0

Cleared

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-Out

PS<2:0>

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note

T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

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