ADM2461EBRWZ-R7 datasheet(17/21 Pages) AD

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Data Sheet

ADM2461E/ADM2463E

Rev. 0 | Page 17 of 21

Figure 41 shows the 8 kV contact discharge current waveform

from the IEC61000-4-2 standard compared to the HBM ESD 8 kV

waveform. Figure 41 shows that the two standards specify a

different waveform shape and peak current (IPEAK). The IPEAK

associated with an IEC61000-4-2 8 kV pulse is 30 A, whereas

the corresponding IPEAK for HBM ESD is more than five times

less at 5.33 A. The other key difference between the two standards

is the rise time of the initial voltage spike. The IEC61000-4-2

ESD waveform has a faster rise time of 1 ns compared to the

10 ns associated with the HBM ESD waveform. The amount of

power associated with an IEC ESD waveform is greater than that of

an HBM ESD waveform. The HBM ESD standard requires the

EUT to be subjected to at least three positive and three negative

discharge tests, whereas the IEC ESD standard requires the EUT to

be subjected to at least 10 positive and 10 negative discharge tests.

The ADM2461E/ADM2463E are rated to ≥±12 kV contact ESD

protection and ≥±15 kV air ESD protection between the RS-485

bus pins (A, B, Y, and Z) and the GND2 pin according to the

IEC61000-4-2 standard. The isolation barrier provides ±8kV

contact protection between the bus pins and the GND1 pin. These

devices with IEC61000-4-2 ESD ratings are better suited for

operation in harsh environments when compared to other RS-

485 transceivers that state varying levels of HBM ESD protection.

IPEAK

I30ns

I60ns

30A

90%

16A

IEC 61000-4-2 ESD 8kV

HBM ESD 8kV

5.33A

10%

tR = 0.7ns TO 1ns

30ns

10ns

60ns

TIME

Figure 41. IEC61000-4-2 ESD 8 kV Waveform Compared to

HBM ESD 8 kV Waveform

TRUTH TABLES

Table 14 and Table 15 use the abbreviations defined in Table 13.

VDD1 supplies the DE, TxD, RE, RxD, INV, and INVR pins only.

Table 13. Truth Table Abbreviations

Letter

Description

High level

Indeterminate

Low level

Any state

High impedance (off)

Table 14. Transmitting Truth Table

Supply Status

Inputs

Outputs

VDD1

VDD2

TxD

INV

A or Y

B or Z

Off

Table 15. Receiving Truth Table

Supply Status

Inputs

Outputs

VDD1

VDD2

A − B

INV or INVR

RxD

≥−0.03 V

≤0.03 V

≤−0.2 V

≥0.2 V

0.2 V < A – B < −0.03 V

0.03 V < A – B < 0.2 V

Inputs open or shorted

Off

RECEIVER FAIL-SAFE

The ADM2461E/ADM2463E guarantee a logic high receiver

output when the receiver inputs are shorted, open, or connected to

a terminated transmission line with all drivers disabled. To achieve

a fail-safe logic high output when the receiver inversion feature

is disabled (INV or INVR = 0 V), the receiver input threshold is

set internally between −30 mV and −200 mV. If A – B ≥ −30 mV,

the RxD output is logic high. If A – B ≤ −200 mV, the RxD

output is logic low. To preserve the fail-safe feature when the

receiver inversion feature is enabled (INV or INVR = VDD1), the

inverted receiver input threshold is set internally between 30 mV

and 200 mV. In the case of a terminated bus with all transmitters

disabled, the termination resistor pulls the receiver differential

input voltage to 0 V, which results in a logic high RxD output

with a 30 mV minimum noise margin. This feature eliminates

the need for the external biasing components that are usually

required to implement the fail-safe feature.

These features are fully compatible with external fail-safe

biasing configurations and can be used in applications with

legacy devices that lack fail-safe support and in applications

where additional noise margin is desired. See the AN-960

Application Note, RS-485/RS-422 Circuit Implementation

Guide, for details on external fail-safe biasing.

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