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ADM2461EBRWZ-R7 bảng dữ liệu(PDF) 3 Page - Analog Devices |
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ADM2461EBRWZ-R7 bảng dữ liệu(HTML) 3 Page - Analog Devices |
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3 / 21 page ![]() Data Sheet ADM2461E/ADM2463E Rev. 0 | Page 3 of 21 SPECIFICATIONS All voltages are relative to the respective ground, 1.7 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 5.5 V, TA = TMIN (−40°C) to TMAX (+125°C). All minimum and maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments PRIMARY SIDE SUPPLY CURRENT IDD1 (Q) 0.6 1 mA DE = 0 V IDD1 2 8 mA DE = VDD1 ISOLATED SIDE SUPPLY CURRENT IDD2 (Q) 5 8 mA VDD2 ≤ 3.6 V, DE = 0 V 5 8 mA VDD2 ≥ 4.5 V, DE = 0 V IDD2 6 9 mA VDD2 ≤ 3.6 V, DE = VDD1 6 9 mA VDD2 ≥ 4.5 V, DE = VDD1 ISOLATED SIDE DYNAMIC SUPPLY CURRENT IDD2 (DYN) 58 78 mA VDD2 ≤ 3.6 V, load resistance (RL) = 54 Ω, DE = VDD1, data rate = 500 kbps 100 145 mA VDD2 ≥ 4.5 V, RL = 54 Ω, DE = VDD1, data rate = 500 kbps DRIVER DIFFERENTIAL OUTPUTS Differential Output Voltage, Loaded |VOD2| 2.0 2.5 VDD2 V VDD2 ≥ 3.0 V, RL = 100 Ω, see Figure 31 1.5 2.1 VDD2 V VDD2 ≥ 3.0 V, RL = 54 Ω, see Figure 31 2.1 3.3 VDD2 V VDD2 ≥ 4.5 V, RL = 54 Ω, see Figure 31 Over Common-Mode Range |VOD3| 1.5 2.1 VDD2 V VDD2 ≥ 3.0 V, −7 V ≤ common-mode voltage (VCM) ≤ +12 V, see Figure 32 2.1 3.3 VDD2 V VDD2 ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 32 Δ|VOD2| for Complementary Output States Δ|VOD2| 0.2 V RL = 54 Ω or 100 Ω, see Figure 31 Common-Mode Output Voltage VOC 1.5 3.0 V RL = 54 Ω or 100 Ω, see Figure 31 Δ|VOC| for Complementary Output States Δ|VOC| 0.2 V RL = 54 Ω or 100 Ω, see Figure 31 Short-Circuit Output Current IOS −250 +250 mA −7 V < output voltage (VOUT) < +12 V Output Leakage Current (Y, Z)1 IO 1 50 μA DE = RE = 0 V, VDD2 = 0 V or 5.5 V, input voltage (VIN) = 12 V −50 +10 μA DE = RE = 0 V, VDD2 = 0 V or 5.5 V, VIN = −7 V Pin Capacitance (A, B, Y, Z) CIN 28 pF VIN = 0.4sin(10πt × 106) RECEIVER DIFFERENTIAL INPUTS Differential Input Threshold Voltage, Noninverted VTH −200 −125 −30 mV −7 V < VCM < +12 V, INV or INVR = 0 V Differential Input Threshold Voltage, Inverted 30 125 200 mV −7 V < VCM < +12 V, INV or INVR = VDD1 Input Voltage Hysteresis VHYS 25 mV −7 V < VCM < +12 V Input Current (A, B) II 167 μA DE = 0 V, VDD2 = 0 V or 5.5 V, VIN = 12 V −133 μA DE = 0 V, VDD2 = 0 V or 5.5 V, VIN = −7 V Pin Capacitance (A, B) CIN 4 pF VIN = 0.4sin(10πt × 106) DIGITAL LOGIC INPUTS Input Low Voltage VIL 0.3 × VDD1 V DE, RE, TxD, INV, INVR Input High Voltage VIH 0.7 × VDD1 V DE, RE, TxD, INV, INVR Input Current II −2 +0.01 +2 μA DE, RE, TxD, VIN = 0 V or VDD1 −2 +10 +30 μA INV, INVR, VIN = 0 V or VDD1 RxD DIGITAL OUTPUT Output Voltage Low VOL 0.4 V VDD1 = 3.6 V, output current (IOUT) = 2.0 mA, differential input voltage (VID) ≤ −0.2 V 0.4 V VDD1 = 2.7 V, IOUT = 1.0 mA, VID ≤ −0.2 V 0.2 V VDD1 = 1.95 V, IOUT = 500 μA, VID ≤ −0.2 V |
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