QPC3614

75Ω 5 −1500MHz Digital Step Attenuator

Data Sheet Rev. D, Feb 28, 2018 | Subject to change without notice

- 13 of 19 -

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Pad Configuration and Description

Top View

Pin

Label

Description

1

C16

16dB Parallel Control Bit

2

RFIN

RF Input Pin: Incident RF power must enter this pin for rated thermal performance and reliability. Do not apply

DC power to this pin. Pin may be DC grounded externally and is grounded through resistors.

3

DATA

Serial Bus Data Input

4

CLK

Serial Bus Clock Input

5

LE

Latch Enable: The leading edge of signal on LE causes the attenuator to change state for serial and latched

parallel modes. For direct parallel mode keep LE at logic high level.

6

VDD

Supply Voltage

7

NC

No Connection

8

NC

No Connection

9

VDD

Supply Voltage

10

GND

Ground Pin

11

GND

Ground Pin

12

VSS

External Negative Supply Voltage. Ground VSS pin to use internal negative voltage generator

13

PBAR/S

Mode Select Pin, Logic Low = Parallel, Logic High = Serial

14

RFOUT

RF Output Pin: Pin may be DC grounded externally and is grounded thru resistors internal to the part.

15

C8

8dB Parallel Control Bit

16

C4

4dB Parallel Control Bit

17

C2

2dB Parallel Control Bit

18

GND

Ground Pin

19

C1

1dB Parallel Control Bit

20

C0.5

0.5dB Parallel Control Bit

Backside Paddle

RF/DC GND

RF/DC ground. Use recommended via pattern to minimize inductance and thermal resistance. See PCB

Mounting Pattern for suggested footprint.

19

1

2

3

4

18

17

16

14

13

12

11

6

7

8

9

6-BIT DSA

LOGIC CONTROL

C16

RFIN

DATA

CLK

C8

RFOUT

PBAR/S

VSS

5

10

15

20

LE

GND