SST25PF040C datasheet(12/47 Pages) MICROCHIP

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SST25PF040C

DS20005397F-page 12

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5.3

Fast-Read Dual Output (40 MHz)

The Fast-Read Dual-Output (3BH) instruction outputs

data up to 40 MHz from the SIO0 and SIO1 pins. To ini-

tiate the instruction, execute an 8-bit command (3BH)

followed by address bits A23-A0 and a dummy byte on

SI/SIO0. Following a dummy cycle, the Fast-Read

Dual-Output instruction outputs the data starting from

the specified address location on the SIO1 and SIO0

lines. SIO1 outputs, per clock sequence, odd data bits

D7, D5, D3, and D1; and SIO0 outputs even data bits

D6, D4, D2, and D0. CE# must remain active-low for

the duration of the Fast-Read Dual-Output instruction

cycle. See Figure 5-3 for the Fast-Read Dual-Output

sequence.

The data output stream is continuous through all

addresses until terminated by a low-to-high transition

on CE#. The internal address pointer will automatically

increment until the highest memory address is

reached. Once the highest memory address is

reached, the address pointer automatically increments

to the beginning (wraparound) of the address space.

For 4-Mbit density, once the data from address location

7FFFFH has been read the next output will be from

address location 000000H.

FIGURE 5-3:

FAST-READ DUAL OUTPUT SEQUENCE

CE#

SIO

SCK

012 34 5 6 7 8

28 29 30 31

MSb

MODE 3

MODE 0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

0 64

3 1

24-Bit Address

Dummy Cycle

DOUT

MSb

DOUT

MSb

DOUT

MSb

DOUT

N+1

N+2

N+3

IO, Switches from Input to Output

ADD.

15 16

High-Impedance

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