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ADSP-SC583 bảng dữ liệu(PDF) 96 Page - Analog Devices

tên linh kiện ADSP-SC583
Giải thích chi tiết về linh kiện  SHARC Dual-Core DSP with Arm Cortex-A5
PDF  173 Pages
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Trang chủ  http://www.analog.com
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ADSP-SC583 bảng dữ liệu(HTML) 96 Page - Analog Devices

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Rev. B
|
Page 96 of 173
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December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SMC Write Cycle Timing With Reference to SYS_CLKOUT
The following SMC specifications (Table 50 and Figure 16) with respect to SYS_CLKOUT are given to accommodate the connection of
the SMC to programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by
setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3.
Table 50. SMC Write Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00)
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
SMC0_ARDY Setup Before SYS_CLKOUT
14.4
ns
tHARDY
SMC0_ARDY Hold After SYS_CLKOUT
0.7
ns
Switching Characteristics
tDDAT
SMC0_Dx Disable After SYS_CLKOUT
7
ns
tENDAT
SMC0_Dx Enable After SYS_CLKOUT
–2.5
ns
tDO
Output Delay After SYS_CLKOUT1
1 Output pins/balls include SMC0_AMSx, SMC0_ABEx, SMC0_Ax, SMC0_Dx, SMC0_AOE, and SMC0_AWE.
7ns
tHO
Output Hold After SYS_CLKOUT 1
–2.5
ns
Figure 16. SMC Write Cycle Timing With Reference to SYS_CLKOUT Timing
SETUP
CYCLES
PROGRAMMED
WRITE
ACCESS
CYCLES
ACCESS
EXTEND
CYCLE
HOLD
CYCLE
tDO
tHO
SYS_CLKOUT
SMC0_ABEx
SMC0_AWE
SMC0_ARDY
SMC0_Dx
tSARDY
tSARDY
tDDAT
tENDAT
tHARDY
tHO
tDO
tHARDY
SMC0_Ax
SMC0_AMSx



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