MCP7940N-ESLASHMS datasheet(36/58 Pages) MICROCHIP

36 / 58 page

MCP7940N

DS20005010J-page 36

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6.1.3

SRAM/RTCC REGISTER CURRENT

ADDRESS READ

The MCP7940N contains an address counter that

maintains the address of the last byte accessed, inter-

nally incremented by one. Therefore, if the previous

read access was to address n (n is any legal address),

the next current address read operation would access

data from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the MCP7940N issues an Acknowledge and transmits

the 8-bit data word. The host will not acknowledge the

transfer but does generate a Stop condition and the

MCP7940N discontinues transmission (Figure 6-3).

FIGURE 6-3:

SRAM/RTCC CURRENT

ADDRESS READ

6.1.4

SRAM/RTCC REGISTER RANDOM

READ

Random read operations allow the host to access any

memory location in a random manner. To perform this

type of read operation, first the address must be set.

This is done by sending the address to the MCP7940N

as part of a write operation (R/W bit set to ‘0’). After the

address is sent, the host generates a Start condition

following the Acknowledge. This terminates the write

operation, but not before the internal Address Pointer is

set. Then, the host issues the control byte again but

with the R/W bit set to a ‘1’. The MCP7940N will then

issue an Acknowledge and transmit the 8-bit data word.

The host will not acknowledge the transfer but it does

generate a Stop condition which causes the

MCP7940N to discontinue transmission (Figure 6-4).

After a random Read command, the internal address

counter will point to the address location following the

one that was just read.

6.1.5

SRAM/RTCC REGISTER

SEQUENTIAL READ

Sequential reads are initiated in the same way as a

random read except that after the MCP7940N trans-

mits the first data byte, the host issues an Acknowledge

as opposed to the Stop condition used in a random

read. This Acknowledge directs the MCP7940N to

transmit the next sequentially addressed 8-bit word

(Figure 6-5). Following the final byte transmitted to the

host, the host will NOT generate an Acknowledge but

will generate a Stop condition. To provide sequential

reads, the MCP7940N contains an internal Address

Pointer which is incremented by one at the completion

of each operation. This Address Pointer allows the

entire memory block to be serially read during one

operation.

Because the RTCC registers and SRAM are separate

blocks, reading past the end of each block will cause

the Address Pointer to roll over to the beginning of the

same block. Specifically, the Address Pointer will roll

over from 0x1F to 0x00, and from 0x5F to 0x20.

FIGURE 6-4:

SRAM/RTCC RANDOM READ

FIGURE 6-5:

SRAM/RTCC SEQUENTIAL READ

Bus Activity

Host

SDA Line

Bus Activity

Control

Byte

Data

Byte

11 1

Bus Activity

Host

SDA Line

Bus Activity

Control

Byte

Address

Byte

Control

Byte

Data

Byte

S 11 01

11 1

S 1101

111

Bus Activity

Host

SDA Line

Bus Activity

CONTROL

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

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