MCP7940N-ESLASHMS datasheet(35/58 Pages) MICROCHIP

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DS20005010J-page 35

MCP7940N

6.0

ON-BOARD MEMORY

The MCP7940N has 64 bytes of SRAM for general pur-

pose usage. It is retained when the primary power

supply is removed if a backup supply is present and

enabled.

Although the SRAM is a separate block from the RTCC

registers, they are accessed using the same control

byte, ‘1101111X’.

6.1

SRAM/RTCC Registers

The RTCC registers are located at addresses 0x00 to

0x1F, and the SRAM is located at addresses 0x20 to

0x5F. The SRAM can be accessed while the RTCC reg-

isters are being internally updated. The SRAM is not

initialized by a Power-On Reset (POR).

Neither the RTCC registers nor the SRAM can be

accessed when the device is operating off the backup

power supply.

6.1.1

SRAM/RTCC REGISTER BYTE

WRITE

Following the Start condition from the host, the control

code and the R/W bit (which is a logic low) are clocked

onto the bus by the host transmitter. This indicates to

the addressed client receiver that the address byte will

follow after it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte transmit-

ted by the host is the address and will be written into the

Address Pointer of the MCP7940N. After receiving

another Acknowledge bit from the MCP7940N, the host

device transmits the data byte to be written into the

addressed memory location. The MCP7940N stores

the data byte into memory and acknowledges again,

and the host generates a Stop condition (Figure 6-1).

If an attempt is made to write to an address past 0x5F,

the MCP7940N will not acknowledge the address or

data bytes, and no data will be written. After a byte

Write command, the internal Address Pointer will point

to the address location following the one that was just

written.

6.1.2

SRAM/RTCC REGISTER

SEQUENTIAL WRITE

The write control byte, address, and the first data byte

are transmitted to the MCP7940N in the same way as

in a byte write. But instead of generating a Stop condi-

tion, the host transmits additional data bytes. Upon

receipt of each byte, the MCP7940N responds with an

Acknowledge, during which the data is latched into

memory and the Address Pointer is internally incre-

mented by one. As with the byte write operation, the

host ends the command by generating a Stop condition

(Figure 6-2).

There is no limit to the number of bytes that can be writ-

ten in a single command. However, because the RTCC

registers and SRAM are separate blocks, writing past

the end of each block will cause the Address Pointer to

roll over to the beginning of the same block. Specifi-

cally, the Address Pointer will roll over from 0x1F to

0x00, and from 0x5F to 0x20.

FIGURE 6-1:

SRAM/RTCC BYTE WRITE

FIGURE 6-2:

SRAM/RTCC SEQUENTIAL WRITE

Bus Activity

Host

SDA Line

Bus Activity

Control

Byte

Address

Byte

Data

S 11 01

1 11

Bus Activity

Host

SDA Line

Bus Activity

Control

Byte

Address

Byte

Data Byte 0

Data Byte N

S 11 0 1

111

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