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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADPD4200 bảng dữ liệu(PDF) 90 Page - Analog Devices |
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ADPD4200 bảng dữ liệu(HTML) 90 Page - Analog Devices |
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90 / 93 page  Data Sheet ADPD4200 REGISTER DETAILS analog.com Rev. 0 | 90 of 93 ADC OFFSET REGISTERS Table 35. Register Details Addr Name Bits Bit Name Description Reset Access 0x010E ADC_OFF1_A [15:14] Reserved Reserved. 0x0 R 0x012E ADC_OFF1_B [13:0] CH1_ADC_ADJUST_x Adjustment to ADC Value. This value is subtracted from the ADC value for Channel 1 in Time Slot x. Set to 0 for chop and float modes. 0x0 R/W 0x014E ADC_OFF1_C 0x016E ADC_OFF1_D 0x018E ADC_OFF1_E 0x01AE ADC_OFF1_F 0x01CE ADC_OFF1_G 0x01EE ADC_OFF1_H 0x020E ADC_OFF1_I 0x022E ADC_OFF1_J 0x024E ADC_OFF1_K 0x026E ADC_OFF1_L 0x010F ADC_OFF2_A 15 ZERO_ADJUST_x Additive Offset for Signal Value. Set to 1 to add 2048 to the signal value prior to clipping positive. 0x0 R/W 0x012F ADC_OFF2_B 14 Reserved Reserved. 0x014F ADC_OFF2_C [13:0] CH2_ADC_ADJUST_x Adjustment to ADC Value. This value is subtracted from the ADC value for Channel 2 in Time Slot x. Set to 0 for chop and float modes. 0x0 R/W 0x016F ADC_OFF2_D 0x018F ADC_OFF2_E 0x01AF ADC_OFF2_F 0x01CF ADC_OFF2_G 0x01EF ADC_OFF2_H 0x020F ADC_OFF2_I 0x022F ADC_OFF2_J 0x024F ADC_OFF2_K 0x026F ADC_OFF2_L OUTPUT DATA REGISTERS Table 36. Register Details Addr Name Bits Bit Name Description Reset Access 0x002F FIFO_DATA [15:0] FIFO_DATA FIFO Data Port. 0x0 R 0x0030 SIGNAL1_L_A [15:0] SIGNAL1_L_A Signal Channel 1 lower half Time Slot A 0x0 R 0x0031 SIGNAL1_H_A [15:0] SIGNAL1_H_A Signal Channel 1 upper half Time Slot A 0x0 R 0x0032 SIGNAL2_L_A [15:0] SIGNAL2_L_A Signal Channel 2 lower half Time Slot A 0x0 R 0x0033 SIGNAL2_H_A [15:0] SIGNAL2_H_A Signal Channel 2 upper half Time Slot A 0x0 R 0x0034 DARK1_L_A [15:0] DARK1_L_A Dark Channel 1 value lower half Time Slot A 0x0 R 0x0035 DARK1_H_A [15:0] DARK1_H_A Dark Channel 1 value upper half Time Slot A 0x0 R 0x0036 DARK2_L_A [15:0] DARK2_L_A Dark Channel 2 value lower half Time Slot A 0x0 R 0x0037 DARK2_H_A [15:0] DARK2_H_A Dark Channel 2 value upper half Time Slot A 0x0 R 0x0038 SIGNAL1_L_B [15:0] SIGNAL1_L_B Signal Channel 1 lower half Time Slot B 0x0 R 0x0039 SIGNAL1_H_B [15:0] SIGNAL1_H_B Signal Channel 1 upper half Time Slot B 0x0 R 0x003A SIGNAL2_L_B [15:0] SIGNAL2_L_B Signal Channel 2 lower half Time Slot B 0x0 R 0x003B SIGNAL2_H_B [15:0] SIGNAL2_H_B Signal Channel 2 upper half Time Slot B 0x0 R 0x003C DARK1_L_B [15:0] DARK1_L_B Dark Channel 1 value lower half Time Slot B 0x0 R 0x003D DARK1_H_B [15:0] DARK1_H_B Dark Channel 1 value upper half Time Slot B 0x0 R 0x003E DARK2_L_B [15:0] DARK2_L_B Dark Channel 2 value lower half Time Slot B 0x0 R 0x003F DARK2_H_B [15:0] DARK2_H_B Dark Channel 2 value upper half Time Slot B 0x0 R |
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