AD4697BCPZ datasheet(82/107 Pages) AD

82 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

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Rev. 0 | 82 of 107

Figure 125. SPI Synchronization with Busy and Alert Indicators

SPI Peripheral Synchronization in Autocycle

Mode

If autocycle mode is enabled when the AD4697/AD4698 enter con-

version mode, the convert start instructions for the ADC core are

generated by an internal oscillator (see the Autocycle Mode sec-

tion). Autocycle mode is therefore ideal for autonomous conversion

applications, where the digital host is idle or in a sleep state until a

user programmed threshold detection event occurs as described in

the Threshold Detection and Alert Indicators section.

The digital host SPI must not attempt to read and write data while

the AD4697/AD4698 are still in the conversion phase. In autocycle

mode, the convert start signal is generated internally, and the digital

host must therefore reference either the busy indicator or the alert

indicator via the general-purpose pin(s) to synchronize the AD4697/

AD4698 and digital host SPIs and ensure that the SPI frames occur

between ADC conversion phases. Figure 103 shows the required

SPI frame timing relative to the busy indicator and alert indicator

when autocycle mode is enabled.

The configurations in Figure 124 and Figure 125 are recommended

when utilizing autocycle mode to achieve synchronization between

the AD4697/AD4698 internal conversion timing and the host SPI

peripheral.

The busy indicator can be used to trigger an interrupt service

routine to read the most recent conversion result and send the 5-bit

SDI commands (see Table 18). The busy indicator transitions low at

the end of each conversion phase and transitions high at the start

of each next conversion phase. The digital host must begin the SPI

frame following the busy indicator falling edge, and the SCK rate

must be sufficiently fast to complete the SPI frame at least 80 ns

prior to the next busy indicator rising edge to conform to the tSCKCNV

specification in Figure 103 and Table 2 (see the Conversion Mode

SPI Clock Frequency Requirements section). The time duration

between busy indicator falling edge and rising edge is given by the

tACBSY specification in Table 2.

The alert indicator can be used as a one-shot trigger for an interrupt

service routine on the digital host to instruct the host SPI peripheral

to send the register configuration mode command and poll the

alert registers (see Figure 124). The alert indicator state is updated

following the completion of the conversion phase. Therefore, an

alert indicator rising edge can signify to the digital host that the

AD4697/AD4698 SPI is ready for an SPI frame. However, the alert

indicator only transitions when a threshold violation is detected on

a given channel, and therefore, the digital host is not able to read

conversion results except for those that cause the alert indicator to

go high (see the Alert Indicator on General-Purpose Pins section).

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