AD4697 datasheet(51/107 Pages) AD

51 / 107 page

Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 51 of 107

Figure 93 shows a timing diagram for the SPI when the AD4697/

AD4698 are in register configuration mode. See Table 2 for the

timing specifications pictured in Figure 93.

high, the SCK edges are ignored, and the SDO is high impedance.

A falling edge on CS begins an SPI frame and data on the SDI is

latched on the SCK rising edges while data is shifted out on the

SDO on the SCK falling edges. A rising edge on CS ends the SPI

frame and forces the SDO to high impedance.

The first phase of an SPI frame immediately following a CS falling

edge is the instruction phase. The instruction phase is followed by

the data phase. For SPI read transactions, the register contents

are shifted out on the SDO during the data phase. For SPI write

transactions, the register contents are latched in on the SDI during

the data phase. See the Streaming Mode and Single Instruction

Mode sections for a detailed description of the order of instruction

and data phases in each SPI frame.

The length of the address in the instruction phase (represented by

M in Figure 93) is set by the ADDR_LEN bit in the SPI_CONFIG_B

The length of the data phase (represented by N in Figure 93)

depends on whether the CRC is enabled and the length of the reg-

ister being accessed (see the Checksum Protection and Multibyte

The AD4697/AD4698 ignore the state of CNV when in register con-

figuration mode. The Entering Conversion Mode section describes

the process for placing the AD4697/AD4698 in conversion mode.

Entering Conversion Mode

To place the AD4697/AD4698 in conversion mode, set

the SPI_MODE bit in the setup register to 1. When the SPI_MODE

bit is set to 1, the SPI frame immediately terminates, and the device

enters conversion mode. No further register reads or writes can

occur until the device enters register configuration mode again.

The digital host must provide a delay specified by tSCKCNV after

the final SCK rising edge of the register write before initiating

conversions with a CNV rising edge (see Table 2 and Figure 93).

Figure 93. Register Configuration Mode Timing Diagram

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