M64893AFP/AGP

SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

MITSUBISHI BIPOLAR DIGITAL ICs

MITSUBISHI

-12

Test mode data set up method

The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls.

(1) When transferring 3-wire 27 bit data

(2) Test Mode Bit Set Up

X

:Random, 0 or 1.normal "0"

CP

:Set up the charge pump current value

T0, T1,&T2

:Set up test modes

RSa, Rsa

:Set up for the reference Frequency division ratio

OS

:Set up the tuning amplifier

S I

:1 Only (It is prohibit to "0 ")

Setting up the charge pump current of the phase comparator

CP

0

1

Mode

Test

Normal

Charge pump current

70 uA

270 uA

T2

T1

T0

0

0

X

0

1

X

1

1

0

1

1

1

1

0

0

1

0

1

Charge pump

Normal operation

High impedance

Sink

Source

High impedance

High impedance

12 pin output

LD

LD

LD

LD

f1/N

Mode

Normal operation

Test mode

Test mode

Test mode

Test mode

Test mode

Setting up for the test mode

ENA

1

19 20

27

SI

CP T2

T1

TO RSa RSbOS

TEST DATA SETTING

READ INTO LATCH

CLK

BAND SW

DATA

M COUNTER DIVISION

RATIO SETTING

S COUNTER

DIVISION RATIO

SETTING

4